The semiconductor industry continually faces challenges in achieving efficient and accurate design and simulation of semiconductor devices. While Atlas TCAD offers a robust platform for semiconductor device simulation, there is a need to seamlessly integrate this simulation environment with the Cadence Virtuoso design tool. The current lack of integration poses limitations on the efficient translation of simulated device characteristics to the design phase. Therefore, the primary problem addressed by this study is the absence of a streamlined process for linking semiconductor devices simulated in Atlas TCAD to Cadence Virtuoso using a Verilog-a model.

This study aims to develop and demonstrate an integrated approach that not only designs and simulates semiconductor devices accurately in Atlas TCAD but also establishes a seamless connection to Cadence Virtuoso through the implementation of a Verilog-a model. The successful resolution of this problem will enhance the overall design and simulation workflow in semiconductor device development, ultimately contributing to improved efficiency and accuracy in the semiconductor industry.

Goal 1

Design and simulate a semiconductor device in Atlas TCAD.

Purpose: The first goal involves designing and simulating a semiconductor device in Atlas TCAD. The objective is to gain in-depth insights into the behaviour of the device for subsequent integration with Cadence Virtuoso.

Method: The process includes specifying device geometry, biasing, and physics-based models, and device simulations. 

Milestones

To contribute and publish select a pending milestone.

Completed

There are no completed milestones.

Pending
Defining semiconductor device geometry for simulation in Atlas TCAD
Optimising biasing conditions for semiconductor device simulation on Atlas TCAD
Implementing physics-driven models on semiconductor device using Atlas TCAD
Executing comprehensive process and semiconductor device simulation in Atlas TCAD
Goal 2

Link the semiconductor device simulated in TCAD to Cadence Virtuoso using a Verilog-a model.

Purpose: The second goal focuses on linking the TCAD-simulated semiconductor device to Cadence Virtuoso using a Verilog-a model. Successful completion of this goal will facilitate a comprehensive understanding of semiconductor device design and simulation workflows.

Method: This involves creating an accurate Verilog-a model, integrating it with Cadence, and validating the device's performance within the Virtuoso environment. 

Milestones

To contribute and publish select a pending milestone.

Completed

There are no completed milestones.

Pending
Developing a Verilog-A model aligned with Atlas TCAD simulations for semiconductor device
Integrating Verilog-A Model with Cadence Virtuoso for semiconductor device simulation
Conducting consistency checks through simulations in Cadence Virtuoso for semiconductor device simulation